发明名称 POLISHING METHOD FOR SEMICONDUCTOR WAFER
摘要 PURPOSE:To drastically reduce the generation of the crack, chip, etc., of a wafer at the initial stage of polishing, by polishing with the polishing pressure being set lower at the initial stage of polishing. CONSTITUTION:Pressure is concentrically applied only on few wafers in a large thickness at the initial stage of polishing and at this time polishing is performed by setting the polishing pressure lower than the ordinary. So, no excessive pressure is applied on these wafers and the inconvenience generation of crack, chip, etc., can be restrained. At the later stage of polishing the thicknesses of each wafers are aligned and the state of the pressure being applied uniformly is obtained. Consequently, the polishing pressure on the whole is set at the specific value higher than that at the initial stage and the averaged pressure applied on the wafer becomes in an adaptive size.
申请公布号 JPH042466(A) 申请公布日期 1992.01.07
申请号 JP19900099106 申请日期 1990.04.13
申请人 SUMITOMO ELECTRIC IND LTD 发明人 NAKAYAMA MASAHIRO
分类号 B24B37/00;B24B37/005;H01L21/304 主分类号 B24B37/00
代理机构 代理人
主权项
地址