发明名称 |
SOI layout for low resistance gate |
摘要 |
Silicon-on-insulator mesa steps cause high resistance in polycrystalline material because of the lack of silicide coverage. In a gate or word line, for instance, this accounts for a large resistance. By connecting the mesas through the body nodes of adjacent transistors, all mesa steps in a polycrystalline semiconductor gate are eliminated. Thus, gate or word line resistance is reduced.
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申请公布号 |
US5079604(A) |
申请公布日期 |
1992.01.07 |
申请号 |
US19910708117 |
申请日期 |
1991.05.29 |
申请人 |
TEXAS INSTRUMENTS INCORPORATED |
发明人 |
HOUSTON, THEODORE W.;BLAKE, TERENCE G. W. |
分类号 |
H01L27/12 |
主分类号 |
H01L27/12 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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