发明名称 |
METHOD AND APPARATUS FOR ASYNCHRONOUS PROCESSOR BASED ON CLOCK DELAY ADJUSTMENT |
摘要 |
A clock-less asynchronous processing circuit or system is configured to operation in a plurality of modes. In an initialization mode (e.g., reset, initialization, boot up), a self-clocked generator associated with the asynchronous circuit is configured to generate an active complete signal (to latch output processed data) within a first period of time after receiving a trigger signal. In a normal mode, the self-clocked generator is configured to generate the active complete signal within a second period of time after receiving the trigger signal. In one embodiment, during the initialization mode, the asynchronous circuit latches the output slower than when in the normal mode. |
申请公布号 |
EP3031137(A1) |
申请公布日期 |
2016.06.15 |
申请号 |
EP20140842900 |
申请日期 |
2014.09.08 |
申请人 |
HUAWEI TECHNOLOGIES CO., LTD. |
发明人 |
TONG, WEN;GE, YIQUN;ZHANG, QIFAN;SHI, WUXIAN;HUANG, TAO |
分类号 |
H03K19/096 |
主分类号 |
H03K19/096 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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