| 摘要 |
PURPOSE:To perform parallel arithmetic at a high speed on the basis of pipeline processing by providing a direct memory access mode wherein cyclic operation is performed while plural access operation timing points are regarded as one set. CONSTITUTION:An input buffer 41 is stored with data fetched from at least two memory areas. When data processing is performed, the data inputted to the circuit 41 synchronously with data fetched by direct memory access DMA is sent out to an arithmetic circuit 40 at the next timing. Further, the logical arithmetic part in the circuit 40 performs multinomial parallel progressive arithmetic among data set in plural registers, i.e. pipeline processing, and the result is stored in an output data buffer 42. This data is returned to the storage area of a general memory by using some of the access timing of an address generating circuit 43. Thus, DMA access control is performed to perform parallel arithmetic at a high speed. |
