| 摘要 |
<p>A semiconductor memory device comprising a memory cell array having a plurality of dynamic memory cells (MCi), each of the memory cells including a plurality of MOS transistors (Q1 - Q4) connected by cascade connection, capacitors (C1 - C4) for storing data each having an end connected to an end of a corresponding one of the MOS transistors, and a register arranged in a column portion of the memory cell array, for temporarily registering the data read from the memory cells in a time series manner. <IMAGE></p> |
