Self-centring data recovery circuit for signal receiver - uses flip=flop receiving input signal and clock signal provided by phase regulating loop

摘要

The data recovery circuit uses a phase-regulating loop (MP2,FS,CO) which multiplies the input signal (IN) with a delayed version of the input signal (IN) to provide a clock signal (TS) supplied directly to a flip-flop (FF1) receiving the input signal (IN) at its data input (D). - The delayed version of the input signal (IN) is provided via 2 series delay elements (DL1,DL2) each with a half delay interval, the first multiplier (MP1) supplying an output to a second multiplier (MP2) receiving a second input from a third multiplier (MP3) receiving a delayed clock signal (TS) and the input signal (IN).