Method for fabricating a mesa transistor-trench capacitor memory cell structure.

摘要

A method is described for fabricating a DRAM cell in a monocrystalline substrate wherein the cell includes an FET transistor (22) and a capacitor (28). The method includes the steps of providing a buried storage capacitor (28) in a trench in the substrate (30, 65); forming a semiconductor mesa area juxtaposed to the buried storage capacitor (28); opening a channel to a contact (32) of the storage capacitor (28); depositing a semiconductor layer (36) over the mesa area and in the opened channel; removing a substantial portion of the semiconductor layer (36) while leaving at least a connecting portion (26) of the semiconductor layer (36) deposited in the channel and in communication with the semiconductor mesa; and forming an FET gate structure (38, 14) including a source and drain (20, 24) on the mesa whereby the connecting conductive portion (26) provides a conductive path between the FET (22) and the capacitor (28). <IMAGE>