MEANS OF PLANARIZING INTEGRATED CIRCUITS WITH FULLY RECESSED ISOLATION DIELECTRIC,申请号EP19910108982-传众专利搜索

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发明名称	MEANS OF PLANARIZING INTEGRATED CIRCUITS WITH FULLY RECESSED ISOLATION DIELECTRIC
摘要
申请公布号	EP0461498(A3)	申请公布日期	1992.01.02
申请号	EP19910108982	申请日期	1991.06.01
申请人	NATIONAL SEMICONDUCTOR CORPORATION	发明人	PIERCE, JOHN M.;AHN, SUNG TAE
分类号	H01L21/304;H01L21/3105;H01L21/76;H01L21/762;(IPC1-7):H01L21/76;H01L21/321	主分类号	H01L21/304
代理机构		代理人
主权项
地址

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