| 摘要 |
<p>An emitter coupled logic circuit includes a differential amplifier circuit (Q11,Q12) provided between a higher potential source (GND) and a first lower potential source (VEE); an emitter follower first transistor (Q1) whose base is connected to a first output node of the differential amplifier, whose collector is connected to the higher potential source, and whose emitter is connected to an output node (OUT); a second transistor (Q2) whose collector is connected to the higher potential source, whose emitter is connected to a second lower potential (VT) having its potential higher than that of the first lower potential and whose base is connected to its collector through a resistor (R1); and a pull-down third transistor (Q3) whose collector is connected to the output terminal and whose emitter is connected to the collector of the second transistor through a resistor (R3). The circuit may further include a capacitor (C1) which is connected between the second output node of the differential amplifier and the base of said third transistor. The power consumption of the circuit is reduced and the operation speeds thereof are improved. <IMAGE></p> |
