| 摘要 |
The present invention relates to a delaying detection circuit for time delaying and detecting a phase shift keying modulated digital input signal based on a time delay of the input signal and the comparison of the phase difference between the time delayed input signal and the input signal. The detection circuit is comprised of a synthesis circuit connected to receive output signals of delaying circuits, and includes a unit for synthesizing the input signal and for estimating the value of the input signal in a previous symbol period by one symbol time, and outputting an estimated delay signal. A phase detection circuit is provided, connected to receive the input signal and the estimated delay signal for outputting a demodulated data corresponding to a phase difference between the estimated delay signal and the input signal.
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