| 摘要 |
PURPOSE:To reduce the probability of errorneous detection of a frame synchronizing signal by delaying a correlation check signal in the unit of frame length and outputting a minimum value of an inputted correlation check signal and the delayed correlation check signal. CONSTITUTION:Figure (a) indicates a correlation check signal outputted from a correlation device 44 and figures b, c depict each output of a multi-stage delay circuit 11 and a minimum value arithmetic circuit 12 in the case of N=1. Each of one-dash chain lines in the figures shows a threshold level set to a comparator 45 and when the correlation check signal exceeds the level, it is discriminated that a frame synchronizing signal is detected. As shown in the figures a, b, errorneous detection of a frame synchronizing signal takes place respectively at times t1, t2. However, since the minimum value is extracted from the output of the circuit 12 as shown in the figure (c), the probability of errorneous detection is reduced in other timings than that of a substantial frame synchronizing signal. That is, let the probability of errorneous detecting the frame synchronizing signal at the time t1 be P, the probability is PN<+1> when the information signal is a random signal, then the probability is decreased as the N increases thereby avoiding errorneous detection. |
