发明名称
摘要 PURPOSE:To increase an arithmetic speed through a simple circuit by performing conversion from a binary number to an absolute value or reverse conversion through a (A-1)' arithmetic circuit when conversion from a fixed point number to a floating point number or reverse conversion is performed. CONSTITUTION:When a positive fixed point number is converted into a floating point number, the positive fixed point number X is inputted to an input side firstly. Consequently, the contents of an input sign register 1 is set to 0, and the contents of an input exponent part register are all set to 0, and X is stored in an input mantissa part register 3 to a width of the low-order 32 bits. A floating/fixed point indicating circuit 6, on the other hand, outputs 0, and then the 1st selecting circuit 7 selects the output side of the input mantissa part register 3 and supplies it to an arithmetic circuit 8 and one input side of the 2nd selecting circuit 9. When the number is positive, 0 as the contents of the input sign register 1 is supplied to and stored in an output sign register 13, 0 is supplied to the 2nd selecting circuit 9, and consequently the output of the 1st selecting circuit 7 is selected and supplied to the 3rd selecting circuit 11 and the 4th selecting circuit 12 respectively.
申请公布号 JPH0381174(B2) 申请公布日期 1991.12.27
申请号 JP19840197421 申请日期 1984.09.20
申请人 NIPPON ELECTRIC CO 发明人 SODA YOSHIHISA
分类号 G06F7/00;G06F7/76 主分类号 G06F7/00
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