Test device for an electronic chip.

摘要

A test device (TD1, SC1) operating in emulation mode for functionally replacing a processor (DSP1) of an integrated electronic chip (EC) by an emulating processor (DSP2) coupled thereto via a first scan path (SC1) built arround the processor (DSP1) and accesible via only two terminals (I, O) of the chip. The first scan path is constituted by a string of cells (CC1) connected in series between the two terminals, each cell latching a data bit normally transferred from another circuit, also built on the chip, to the processor thereof. The latched data is then serially transferred to a second scan path (SC2) similar to the first one and built arround the emulating processor. From the second scan path, the data is transmitted to the emulating processor which handles it and returns resulting data to this second scan path. This resulting data is then transferred back to the first scan path from which it is supplied to the other circuit. The transfer of data between the first and second scan paths is performed between each processing step of the emulating processor so that the test is executed in "real time". A variant (TD2, SC1) of this test device discloses the substitution of the emulation processor (DSP2) for an observation processor (DSP3) provided with a third scan path (SC3) built arround it. This test device has a comparator (CMP) for comparing the the results of the observation processor (DSP3) and applied to the third scan path with those of the processor (DSP1) of the chip and available on the second scan path (SC2). <IMAGE>