发明名称 HDTV ENCODER
摘要 PURPOSE:To revise a parallel expansion number with a simple circuit without use of an elastic memory with a large circuit scale by converting a serial code into a required N parallel codes at an S/P converter and sending the code to a transmission line via an interface. CONSTITUTION:A pre-processing section 10 converts an inputted HDTV signal into M-series of serial codes D1-DM and they are given to M-set of prediction coding sections 21, 2M, in which they are subjected to differential coding simultaneously separately. A P/S converter 1 operated by an output CK of a series of clock oscillator 3 converts the M parallel codes into a serial code S. Then an S/P converter 2 converts the serial code S being the output of the P/S converter 1 into desired N parallel codes D11-D1N, which are sent to a transmission line 60 via an interface 50. Without use of an elastic memory EM requiring 2 series of clocks CK1, CK2 in a conventional encoder, the M-series of serial codes D1-DM are converted into the desired N parallel codes D11-D1N and outputted to the transmission line 60.
申请公布号 JPH03296383(A) 申请公布日期 1991.12.27
申请号 JP19900098813 申请日期 1990.04.13
申请人 FUJITSU LTD 发明人 WADA NOBUYUKI;KAWAKADO KOSUKE
分类号 H04N19/423;H04N7/00;H04N7/015;H04N19/00;H04N19/42;H04N19/85 主分类号 H04N19/423
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