| 摘要 |
<p>PURPOSE:To execute both of the reading of an input level and the control of an output level through only one port by temporarily setting up the port to an input mode when a request for inverting an output level is received, reading out the input level, and then setting up the port to the output mode again to invert the output level. CONSTITUTION:The port is usually set up in the output mode, and only when a request for inverting the output level is received, the output mode is temporarily switched to the input mode and the input level concerned is inputted. In the case of setting up the input mode, a DDR register 1 is set up to a high level. Thereby, transistors TR1, TR2 are turned off, the input level is read out, and at the time of inputting a clock signal phi, an AND gate 7 is turned to a high level, a flip flop(FF) 6 is driven, and the FF 6 is inputted to an input register 3 through the port P. Then, the input mode is restored to the output mode to invert the output level.</p> |
