| 摘要 |
PURPOSE:To cope with a glitch unable to be absorbed with a filter, and to prevent synchronizing step-out by absorbing the glitch by generating a short pulse wider than the width of the glitch while synchronizing with the rise of the output of a clock, and on the other hand, delaying the original clock by the rise time of the short pulse, and passing both of them through an AND gate. CONSTITUTION:A pulse generation circuit 10 generating the pulse wider than the width of the glitch at the rise of a demodulation clock, a delay circuit 11 delaying the clock and data output by time required for the pulse to rise, and the AND gate 8 adding the clocks passing through the pulse generation circuit 10 and the delay circuit 11 and generating a new clock are provided. Then, the glitch is absorbed by generating the short pulse wider than the width of the glitch while synchronizing with the rise of the output of the clock, and on the other hand, the original clock is delayed by the rise time of the short pulse, and both of them pass through the AND gate 8. Thus, the glitch can be eliminated by executing digital processing in addition to the filter of an analog circuit. |
