NONVOLATILE SEMICONDUCTOR STORAGE DEVICE

摘要

PURPOSE:To decrease the threshold level distribution of a memory cell by applying a prescribed verification potential to a control gate of the memory cell in an EEPROM employing a memory transistor (TR) in which a charge storage layer and a control gate are laminated so as to confirm a data write state. CONSTITUTION:Memory TRs M1 - M8 each of the charge storage layer and the control gate of which are laminated on a semiconductor substrate are connected in series and TRs S1, S2 are connected in series to form a NAND EEPROM cell. Then a prescribed verify potential is fed to a selected EEPROM cell in a memory cell array 2 from a control gate control circuit 6 to write the cell, and write information from a data latch circuit 5 via an I/O buffer 4 and readout information from a sense amplifier 1 are compared at a data comparator circuit 3 forming a verify control circuit, a threshold level of the EEPROM is confirmed and when the level is not reached to the threshold level. Rewrite is repeated.