| 摘要 |
<p>A signaling mechanism for sending and receiving signals to and from any one of all of a plurality of devices, including peripheral controllers (24) and processors (10), in a multiprocessor system. The signaling mechanism includes two switches, a first switch (480) routing a signal command generated by the device to a signal dispatch logic (460) and a second switch (470) for receiving signals generated by the signal dispatch logic and routing the signals to the selected device. The signal dispatch logic (460) receiving the signal command, decodes the destination select value and generates a signal to be sent to the selected device. The signal command includes a destination select value representing a device selectably determined by the device. The signaling mechanism also includes an arbitration mechanism (51) connected to the signal dispatch logic (460) and the first switch for resolving simultaneous conflicting signal commands issued by two or more devices. The signal generated by the signal dispatch logic (460) may include a plurality of bits representing one or more types of predefined signals to be acted upon by the device.</p> |
