发明名称 Binary signal generating circuit with parallel sample and hold circuits and common sampling switch
摘要 A single sampling switch i provided for a plurality of sample/hold function-equipped comparators. Thus, when the sampling switch is turned on, an analog signal is fed to each sample and hold circuit, and when it is turned off, the analog signal fed in at that time is sampled and held in each sample/hold function-equipped comparator. The analog signal values sampled and held in the sample/hold function-equipped comparators are averaged when the averaging switch is turned on. In this manner, since the timing for sampling and holding is controlled by the single sampling switch, a smaller number of switching elements are sufficient and the possibility of the timing for sampling and holding differing between the sample/hold function-equipped comparators is eliminated.
申请公布号 US5075688(A) 申请公布日期 1991.12.24
申请号 US19900622071 申请日期 1990.12.04
申请人 MITSUBISHI DENKI KABUSHIKI KAISHA 发明人 HOSOTANI, SHIRO;MIKI, TAKAHIRO
分类号 H03M1/36;H03M1/06 主分类号 H03M1/36
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