发明名称 |
Switching state retention circuit having a feedback loop stabilizing capacitance |
摘要 |
An improvement in a switching state retention circuit of adding a shunt capacitance across an inverter output in a selectable feedback loop. The circuit has a controlled inverter connected to both the selectively connected feedback loop and an output inverter. The shunt capacitance is across an inverter in the feedback loop to control propagation delay therearound without slowing state changes at the output of the circuit.
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申请公布号 |
US5075570(A) |
申请公布日期 |
1991.12.24 |
申请号 |
US19870125309 |
申请日期 |
1987.11.25 |
申请人 |
HONEYWELL INC. |
发明人 |
SHEWCHUK, THOMAS J.;MILLS, BILLY D. |
分类号 |
H03K3/356 |
主分类号 |
H03K3/356 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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