| 摘要 |
<p>PURPOSE:To enable use even in a field where high-speed security is needed and high-speed transmission is required by providing a CPU on a single semiconductor chip, a memory accessible only through the CPU, and plural connection terminals. CONSTITUTION:When a command block 20 is transmitted from an external equipment, a synchronizing signal given to a synchronizing signal terminal 9d is triggered to fetch a start code 21. When the start code 21 is a predetermined start code value and a vertical parity is the correct value, block data 22-27 to be transmitted afterwards are received. A horizontal parity 27 calculates the exclusive logic of data from the start code 21 to data just before the horizontal parity 27, to check the vertical parity every time the information of 9 bits is received. After receiving the command block 20, a ciphered data 26 is deciphered to transmit the result to the external equipment as a deciphered data.</p> |
