| 摘要 |
PURPOSE:To obtain a justifying circuit in a floating point adder which can be used in common when there are two kinds of expression formats of input data by adding exponential part and mantissa selecting circuits. CONSTITUTION:The 2nd operand mantissa selecting circuit 23 selects the mantissa of the 2nd operand and sends the selected result to mantissa selecting circuits 50, 51. The circuit 51 selects the mantissa of a larger output from an exponential part comparator 40 and stores the selected result in an adder input data holding circuit 91. The shifted output from a digit shifting circuit 60 is inputted to a bit shifting circuit 70, but since the output of lower two bits from an exponential part subtractor 30 is ''00'', the circuit 70 executes no shifting operation and outputs the input data to an adder input data holding circuit 90 as they are. Since the lower two bits of the subtractor 30 are ''00'', a parity forecasting circuit 80 is not actuated, data shifted by the difference of the exponential part and a parity bit are stored in the circuit 90. The data stored in the circuit 90 are justified with the mantissa of the 2nd operand stored in the circuit 91. |
