| 摘要 |
PURPOSE:To digitize the system overall to obtain a superior characteristic without any temperature drift and little signal distortion and signal error, by discriminating the duty factor of the output signal of a digital phase lock loop (DPLL) digitally. CONSTITUTION:The duty factor of an output signal 10 of a DPLL5 is discriminated digitally in a digital discriminating circuit 12. That is, the zero crossing waveform of a binary frequency deviation modulation signal 9 is inputted to the DPLL5, and the output signal 10 is inputted to the digital discriminating circuit 12, and the duty factor of the output signal is discriminated on a basis of a high-speed sample and its pulse count value. An output 14 of the digital discriminating circuit 12 is inputted to a converting circuit 13 and is not only converted to corresponding DC components by the repeat period of the pulse of the output signal 10 but also outputted to a discriminating circuit 7 through a digital primary low pass filter. The discriminating circuit 7 discriminates whether an output signal 11 is larger than a constant threshold or not, thereby outputting a demodulation data signal 8. |
