发明名称
摘要 Where an N-bit input data is rotated together with a carry bit by an N-bit or more rotate count, the actual rotate count is obtained as a remainder or modulo of x/N+1 (x: rotate count; N: data bit length). The above remainder will not be obtained by simply masking shift signals. Therefore, the remainder is calculated at high speed through hardware including a subtrahend calculator section for calculating (N+1) (i) (i=0, 1, 2, . . . ) and a subtracter section for calculating {x-(N+1) (i)} to obtain a modulo or a remainder representative of an actual rotate count.
申请公布号 JPH0379734(B2) 申请公布日期 1991.12.19
申请号 JP19860226220 申请日期 1986.09.26
申请人 TOKYO SHIBAURA ELECTRIC CO 发明人 TOKUMARU TAKEJI;NAGATA MYUKI
分类号 G06F7/00;G06F5/01;G06F7/76 主分类号 G06F7/00
代理机构 代理人
主权项
地址