| 摘要 |
PURPOSE:To shorten the time for the count execution start of a programmable counter, by providing a gate circuit having a delay circuit of four-gate components in the preceding stage of a D type FF. CONSTITUTION:When an LOAD terminal is set to L and a program data input terminal Pi is set to H, the output of an NAND gate 24 becomes H; and since an NAND gate 26 is H, a transmission gate TG28 is turned on, and a D type FF34 is set to H. Next, the LOAD terminal is set to H; and if a CEP or CET terminal is L, the output of the NAND gate 26 becomes L, and a TG31 is turned on, and the D type FF34, is held in the preceding state. When CEP and CET terminals become H together, the D type FF34 is inverted each time a clock terminal CP becomes H, and thus, count advances. Consequently, the propagation delay time to the count start is shortened to the time of four-gate components of NAND gates 25 and 26, an inverter 27, and the TG28. |
