| 摘要 |
A cell switching system for receiving on a plurality of input lines (I1...In) cells each having a fixed bit length and consisting of data and an address indicative of a destination of the data, in which the cells are so switched that the data are sent to desired destinations, that the date is sent out via a plurality of lines (O1...On), the system including a plurality of time division lines each being associated with respective one of the input lines and having a time division multiplex channel construction associated with one of the output lines, a plurality of serial-to-parallel converting means (111...11n) each being associate with respective one of the input lines for delivering an input cell to associated ones of said time division lines, a plurality of address filter means (121...12n) each being associated with respective one of the input lines for identifying one of the output lines to which a cell is destined on the basis of the address of the cell and indicating a channel position associated with the one output line on associated one of the time division lines, a plurality of rearranging means (131...13n), each being associated with respective one of the input lines for rearranging, in response to an indication from associated one of the address filter means, a plurality of selector means (161...16m) each being associated with a respective one of the output lines, and a plurality of parallel to serial converting means (181...18m) each associated with a respective one of the output lines, the time division lines being related to the channel positions such that only a single channel that corresponds to one of the output lines exists at any one position on a time axis, whereby the cells to be fed out to the same output are prevented from conflicting each other. |
