发明名称 |
Memory address space determination using programmable limit registers with single-ended comparators. |
摘要 |
<p>An apparatus for determining cacheable address and write-protect memory address regions in a computer system which includes a programmable single-ended limit register and a single comparator to determine each such region. A programmable limit register associated with each respective memory address region defines a boundary limit for each of the respective memory regions. A single address comparator associated with each respective limit register determines whether a memory address developed by the computer system resides between the respective boundaries provided by the value stored in the respective programmable limit register and a predefined address. The use of a single limit register and a single address comparator for each memory address region reduces the gate count and decreases the input buffer loading in the logic circuitry. <IMAGE></p> |
申请公布号 |
EP0461924(A2) |
申请公布日期 |
1991.12.18 |
申请号 |
EP19910305420 |
申请日期 |
1991.06.14 |
申请人 |
COMPAQ COMPUTER CORPORATION |
发明人 |
KELLEY, PHILIP CO.;COLLINS, MICHAEL J. |
分类号 |
G06F12/06;G06F12/08 |
主分类号 |
G06F12/06 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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