An improved semiconductor read-only VLSI memory.

摘要

The performance of a hysteresis address input buffer of a VLSI ROM is improved by providing additional driving power to establish the high and low voltage transition points of the input buffer. The address transition detection circuit is improved by holding the previously latched address signal until a predetermined delay after receipt of the new address signal. The operation of signal buffers can be stabilized and the emission electrons avoided by selectively coupling the input to the last stage of the buffer to a predetermined voltage during any precharge hold time interval. The memory array is improved by providing an architecture for the columns of memory cells so that the signal from the address memory cell need propagate only on the diffusion bit lines by a distance no greater and no less than the length of the diffusion bit line within a single block of the memory cells. The architecture of the memory layout is improved by providing bit line and virtual ground line contacts at opposing ends of the memory block and by replicating the memory block through mirror symmetry on the semiconductor substrate. <IMAGE>