| 摘要 |
PURPOSE:To control the synchronized operation of a plurality of pulse motors by only adding one set of CPU with a simple peripheral circuit by effecting the timing operation of respective phase data from an I/O port by a latch circuit. CONSTITUTION:A CPU 1 reads and decodes a program from a ROM 2 and excites pulse motors 16-18 through I/O ports 8, 9, latch circuits 10-12 and drive circuits 13-15. When pulse motors 16, 17 are synchronized, the CPU 1 outputs a phase data, indicating the excitation of a first phase, into the terminals PA, PB of the I/O port 8 and, thereafter, starts a timer circuit 4. The timer circuit 4 generates a timing signal upon finishing counting and requires interruption to the CPU 1 through an interruption controller 5 while phase data are fixed by the latch circuits 10, 11. According to this method, the phase switching of two sets of pulse motors can be effected simultaneously. |
