发明名称 CLOCK REGENERATING CIRCUIT
摘要 PURPOSE:To stably regenerate the clock of a desired wave even when there is the interference of a jamming wave by providing a desired wave degradation detecting means and regenerating the clock according to the clock phase informa tion of a burst just before degradation when the degradation of the desired wave is detected. CONSTITUTION:As the degradation detecting means, a D/U(desire/undesire) detector 28 executes degradation detection according to the increase of error in received data and the dissidence of the identification number of a communica tion party station or the like. When the degradation is detected at an H level at normal time not to detect the degradation, the D/U detection signal at an L level is generated and supplied to a controller 25. When the D/U detection signal is turned to the L level, the clock phase information stored in a memory part 29a or 29b is read out in the next burst signal and supplied to a data selector 27. Then, the clock is regenerated according to the clock phase informa tion of the burst just before the degradation. Thus, even when there is the interference of the jamming wave, the clock of the desired wave can be stably regenerated.
申请公布号 JPH03285430(A) 申请公布日期 1991.12.16
申请号 JP19900086624 申请日期 1990.03.30
申请人 NIPPON TELEGR & TELEPH CORP <NTT> 发明人 TOMA KENJI;TANAKA KIYOSHI;HORIKAWA IZUMI
分类号 H04L7/02 主分类号 H04L7/02
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