| 摘要 |
Frequency multiplier. It supplies at its output a digital signal whose frequency is the frequency of the input signal multiplied by a positive real number, avoiding the use of microprocessors and of phase-synchronisation circuits. It features an up counter 1, which receives on its inputs 5, 7 respectively a first reference signal Fref1 and the input signal Fe, delayed by a delay circuit 6 which is connected with a hold circuit 2. The latter is connected to a programmable down counter 3 and receives the input signal Fe on its input 4. The programmable down counter 3 generates a signal of the desired frequency F1 at its output and receives, on its inputs 9, 8, a second reference signal Fref2 and the output signal F1 itself. Optionally, it may incorporate a comparator 10 connected to the data input and output of the hold circuit 2 in order to obtain a gradual reduction in the frequency of the output signal F1 when an abrupt reduction occurs in the frequency of the input signal Fe. <IMAGE>
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