| 摘要 |
PURPOSE:To easily realize a large delay by means of setting of a counter by obtaining a required delay time made up of a coarse delay in the unit of clock period through the use of the counter, and a fine delay in the clock period through the comparison between a ramp voltage and a reference voltage. CONSTITUTION:When an input pulse is supplied to a counter 23, the count of clocks at a terminal 24 is started and when the counter 23 counts the clocks by a set number (in this case, a coarse delay time is obtained), the output of the counter 23 goes to logical '1', it sets a flip-flop 18 to set its Q output to logical '0', resulting in turning off a switch 14. Then charging of a capacitor 12 at a low current (i) is started, a ramp voltage (v) is generated, the ramp voltage (v) and a variable reference voltage V5 are compared by a comparator 14. When the output of the comparator 14 gets a high level, its output resets the flip-flop 18 and an output pulse of the comparator 14 is outputted to an output terminal 16. |
