CHROMINANCE PROCESSING AND TIMING SYSTEM

摘要

A circuit for compressing and expanding video color component data comprises a FIFO line memory (358) and a delay circuit (540). A timing circuit (339) generates control signals for writing data in the line memory and for reading data from the line memory to compress and expand the data. The delay circuit matches the data compressed or expanded in the FIFO line memory to luminance data which is similarly compressed or expanded. A switching network (534, 536, 538) selectively establishes a first signal path in which the line memory precedes the delay circuit for implementing the data expansion and a second signal path in which the delay circuit precedes the line memory for implementing the data compression. The switching network is controlled according to selected display formats requiring compression or expansion, for example by a microprocessor.