| 摘要 |
<p>First and second field type detectors (702, 710) for first and second video signals have outputs indicating whether the video signals have first or second field types. The first video signal is synchronized with the second video signal for a combined display by a synchronous field memory (350) and an asynchronous multiple line memory (354). The field type of the second video signal is changed when necessary to match the field type of the first video signal to maintain interlace integrity in the combined display. A field type changing circuit (712, 714, 718) which controls the synchronizing, has a first mode of operation which delays writing a current field of the first field type by one horizontal line period, a second mode of operation which advances writing a current field of the second field type by one horizontal line period and a third mode of operation which maintains a current field type. A plurality of selectable interlace correction signals are generated, each being appropriate for one of the plurality of comparison outcomes.</p> |
