| 摘要 |
PURPOSE:To enable a fetching of initial fault analyzing data of elements to be tested and to exactly perform reevaluation of a production line by limiting the writing number of fault analyzing data into fault analyzing memories, to a specified value. CONSTITUTION:Logical sum for fail signals F1a-Fna, F1b-Fnb, F1c-Fnc, F1d-Fnd resulting from the comparison of the outputs for every channel of the plural (e.g., 4 pieces) elements to be tested and the expecting value, are ORed by separate OR circuits 221-224 respectively and supplied to respectively corresponding fault quantity limiting circuits 251-254. The circuits 251-254 are equally constituted, and counters 27 are counted up by the inputted signals indicating the faulty outputs of circuits 221-224, and when the count value attains the specified count value, gates 26 to which the outputs of corresponding circuits 221-224 are being supplied, are closed. Then, the logical sum for the outputs of each gate 32 for the circuits 251-254 is taken by a 2nd combinational circuit (OR circuit) 24, and the signal of circuit 24 indicating the fault in the output is counted 23 and also the fault analyzing data at that time are written in the fault analyzing memories 18a-18c taking the count value as the address. |
