发明名称 METHOD AND APPARATUS FOR MANAGING PAGE ZERO MEMORY ACCESSES IN A MULTI-PROCESSOR SYSTEM
摘要 <p>Apparatus and method for use in a multi-CPU data processing system (10) wherein each CPU (12-18) is coupled to a common bus (20) and through the common bus to a main memory (28). The method and apparatus provides a program, such as an operating system, that is operating upon each of the CPUs access to a page of data within the main memory. Each of the CPUs generates a first address for identifying a memory location or locations within a page of the main memory. The first address is modified as a function of the first address and as a function of an identification of the CPU to generate a second address for identifying a memory location or locations that are either within the same page or within another page of the main memory. The modified address is applied to the memory for accessing the memory location or locations.</p>
申请公布号 WO1991019254(A1) 申请公布日期 1991.12.12
申请号 US1991003479 申请日期 1991.06.05
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