Semiconductor DRAM with matrix of cells coupled to driver leads - has read=out amplifiers connected and selectable by column address

摘要

Several first energising or driver leads (VL,4) are connected for transmission of a first signal to the memory cells, one lead being selectable by a line address. Several energising or driver leads (PL,13) are connected for transmission of a second signal, the lead(s) being selectable by a column address. Several read-out and writing leads (BL,16-1,-2) are also connected to the cells for read-out and writing steps w.r.t. the memory cells. Several read-out amplifiers (20) connected to the read-out and writing leads are selectable by the column address. The memory cells in the column are coupled to the same read-out amplifier via the read-out or writing leads. ADVANTAGE - Short cycle or step time for access operations. Low current requirements.