| 摘要 |
<p>Clock pulses from a master oscillator (10) are distributed in a multiprocessor computer system (17A-17N) so that they arrive at a large number of utilization points (21) located in operating clusters (#1, #2 --- #N) of modules within extremely tight time tolerances of each other. The delays associated with each component (31, 41), electrical or optical connection (25, 34, 47), cable (24, 34, 48) or the like are determined by direct measurement or by using known standard characteristics. A time delay budget for each complete clock pulse path from the point of initial divergence (31) from the master clock source (20) to the final chip delivery point (21, 162) is logged and summed. Components (56, 58) capable of introducing predetermined amounts of time delay are incorporated in some or all clock pulse paths. These components are adjusted so as to balance out the differences determined from the clock path budgets. The clock paths are implemented in electrical components either alone or in combination with optical components (150), or in substantially all optical configurations. One arrangement for controlling optical skew includes an arrangement (145) of optical elements (174, 176, 177) physically displaceable in a coaxial direction relative to one another. Skew adjustment networks employ a unique composition of coarse (56) and fine (58) selectable delay arrays implemented either by electrical components, optical components, or a combination thereof.</p> |
