| 摘要 |
<p>A high-speed circuit that performs unsigned mode, two's complement mode, and two types of mixed mode multiplication-accumulation with equal facility. The circuit is an array (10) constructed from ten different adder elements (FA1S, FA1A, FA2A, FAC, FACA, FACC, FAAC, FAAC3, HAC, and HAC2, which correspond to Figures 13-22, respectively). The array has two multiplier input operands (X and Y) and one accumulator term (Z), the three of which may be expressed as binary power expansions. Final addition of sumout and carryout terms of the array (10) is performed by final adder (11), which may comprise any of several possible adder configurations, including full carry lookahead, carry select, and conditional-sum type adders. Speed is accomplished through the use of high-speed adder elements having few gate delays, and by summing all even array rows together and all odd rows together, then adding the even sum with the odd sum in the final adder (11) using a Wallace tree technique. The circuit incorporates a high degree of regularity and interconnectivity, which facilitates compact circuit layout.</p> |
