LEVEL TRANSFER CIRCUIT

摘要

The level translation circuit for reducing the current flowing to a ground comprises a signal translation circuit (30) connected between FETs (Q3) and (Q6), a first latch circuit (10) connected to a connection point of the FETs (Q1) and (Q2) and for receiving a driving signal from the signal translation circuit (30) and a second latch circuit (20) connected to a connection point of the FETs (Q4) and (Q5) and for receiving a driving signal from the signal translation circuit (30). The first and second latch circuit (10,20) are driven alternatively in response to a control signal (Vi). The FETs (Q3) and (Q6) are not driven at the same time.