| 摘要 |
PURPOSE:To reduce the circuit scale of a frame synchronization circuit by connecting one input output terminal of a synchronizing pulse information memory to an input of a shift register and connecting outputs of a prescribed number sequentially in parallel with a synchronizing pulse detection section. CONSTITUTION:Time slots B1-B7 latching frame synchronizing pulses F1-F7 are arranged continuously to one terminal IO1 of a synchronizing pulse information memory 7. when the pulses F1-F7 are inputted to time slots B1-B7, a register 2 outputs sequentially the pulses F1-F7 to output terminals O11-O17. Thus, the pulses F1-F7 are sequentially outputted to the output terminals O11-O17 at a specific period. A synchronizing pulse detection section 3 takes a point of time when the pulses F1-F7 are sequentially outputted from the register 2 as a prescribed period to detect the coincidence of the pulse. Thus, the scale of the frame synchronizing circuit is reduced. |
