发明名称 SEMICONDUCTOR MEMORY DEVICE
摘要 PURPOSE:To improve the versatility of a chip by processing an optional bit in accordance with presence or absence of the disconnection of a fuse in one chip. CONSTITUTION:In when a chip is operated as 8 bits, a fuse F11 is not disconnected. Thereby, an output circuit corresponding to the 9th bit is inactivated. When the chip is operated as 9 bits, the fuse F11 is disconnected. Thereby, the level of a node N12 is turned to a VCC level through an inverter circuit 17 at the time of turning on a power supply. The level of the node N2 is inverted by an inverter circuit 111 and a GND level is inputted to NOR circuits 18, 19, which are functioned as inverter circuits. The level of a node N17 is turned to the same level as that of a DOE signal and an output circuit 1A acts similarly to a normal output circuit. The level of a node N16 is turned to the same level as that of a signal, the inverse of CS' and the input circuit 1B of the 9th bit acts as a normal input circuit.
申请公布号 JPH03280296(A) 申请公布日期 1991.12.11
申请号 JP19900079221 申请日期 1990.03.28
申请人 NEC CORP 发明人 MORIKAMI SEIICHI
分类号 G11C11/413 主分类号 G11C11/413
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