| 摘要 |
PURPOSE:To reduce the area of memory cell of a bipolar ECL, by forming the emitter, the base and the collector of a PNP transistor in the same aperture, forming a P<-> type semiconductor layer on the collector, forming a multi-emitter in the same layer, and constituting a base collector intersecting connection wiring of the NPN transistor. CONSTITUTION:A semiconductor substrate wherein an N<+> type buried layer 2a and an N<-> type semiconductor layer 3a are epitaxially grown on a P<-> type semiconductor substrate 1a is prepared; a P<+> type impurity layer 5, a P<-> type impurity layer 4a and an N<+> type semiconductor layer 6 are formed by introducing impurities; a silicon oxide film 13 is grown on the upper layer, and selective etching is performed. Next, a P<-> type epitaxial layer 15 is selectively grown in the aperture, and P<-> type semiconductor layers 8, 9 are formed. Both ends of the P<-> type semiconductor layer 9 are connected between the collector and the base of PNP transistors forming a pair, and constitute an intersecting connection between both transistors. Polycrystalline silicon films 11, 10a are laminated on the upper layer of the P<-> type semiconductor layer 9, and N<+> diffusion is performed, thereby forming the emitters of the NPN transistors. |
