| 摘要 |
A general architecture to correct conversion errors of a multi-stage, pipelined subranging analog-to-digital (A/D) converter includes cascaded stages, (1, 2 ....m), each stage generating (12) a binary conversion signal representing the nearest quantized level below that of the analog input signal and also generating (14,16,18) a residual analog signal applied to the next conversion stage. The binary conversion signals from the several stages address individual or common look-up tables (30) providing compensated binary signals selected to compensate for nonidealities of the A/D converter components. The compensated binary signals from the look-up tables provide a corrected output signal when summed together (32). A simple method of calibration for the A/D converter makes use of a least-mean-squared adaptation algorithm. The A/D converter accommodates practical circuit nonidealities such as component mismatching, gain error and voltage offsets, and handles high levels of amplifier nonlinearity. The architecture is applicable to any subranging converter with arbitrary numbers of stages and bits per stage. <IMAGE>
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