| 摘要 |
<p>PURPOSE:To allow only the software of the system to cope with a format of a line reception data by providing a processing means in the inside of a CPU and implementing synchronization check, inversion consecutive transmission collation and parity check. CONSTITUTION:A line reception data is demodulated into a serial data through a demodulation section DM 1 and a reception timing extraction section TMD 3 extracts a reception timing by a change point and a reception clock. A demodulated serial data is written in an n-bit serial-in parallel-out shift register SHR 2 in the reception timing. Then an n-bit data is written in an n-bit latch 4 and fetched in a CPU 6 after n-bit count. Then the processing means in the inside of the CPU 6 executes processing of synchronization check, inversion consecutive transmission collation and parity check. Then the hardware is standardized and the revision of the software is enough to cope with the format revision in the line reception data.</p> |
