发明名称 METHOD FOR ANALYZING DATAPATH ELEMENTS
摘要 According to a technique for determining delays through multi-stage datapath elements, estimates of the delays through each stage of the datapath element are computed in accordance with an equation such as: Ds=DbNb+C; where Ds is the estimated stage delay, Db is a delay associated with communication between bits in the stage, Nb is the number of bits in the datapath element, and C is a constant. The estimated stage delays are used to determine positions of pipelining stages in the datapath element.
申请公布号 GB2244829(A) 申请公布日期 1991.12.11
申请号 GB19910014332 申请日期 1991.07.03
申请人 * VLSI TECHNOLOGY INC 发明人 CREIGHTON SATOSHI * ASATO;SURESH KISHORBHAI * DHOLAKIA;CHRISTOPH * DITZEN
分类号 G06F7/53;G06F7/00;G06F7/506;G06F7/527;G06F9/38;G06F17/50 主分类号 G06F7/53
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