| 摘要 |
PURPOSE:To improve the general-purpose performance of the circuit by applying phase-locked operation to a signal from an optional frequency signal source and using a tuner so as to extract a stable clock. CONSTITUTION:An input signal from a frequency signal source 1 is inputted to a comparator circuit 21 in a digital PLL circuit 2, in which phase-locking is implemented. A variable frequency divider 22 in the circuit 2 revises a frequency division ratio corresponding to the input signal frequency and inputs its output to the comparator circuit 21. The circuit 2 applies phase locking to an optional frequency. Then an output signal of the comparator circuit 21 is inputted to a fixed frequency divider 3, where the signal is frequency-divided and phase fluctuation is suppressed in the signal by a tuner 4 and a resulting clock is extracted. Thus, the general-purpose performance of the circuit is attained. |
