| 摘要 |
A power splitter (10), including a feedback amplifier (16) and matching network (18), is disclosed for splitting the output of a signal source (12) to be applied to a processing system (14). The feedback amplifier includes a gain stage (20) and active load (22). The gain stage includes a field-effect transistor (FET) (Q1) and feedback components (LF and RF) that provide the amplification required to give the power splitter unity gain. An inductive element (LD) gives the amplifier the desired bandwidth and a dual-gate FET (Q2) is employed as the active load to reduce loading of the gain stage. The matching network includes a plurality of stages (e.g., 24), each of which includes a source follower FET (e.g., Q3 ) and a single-gate active load FET (e.g., Q4). The resultant power splitter provides the desired equal power, matched phase outputs with suitable isolation and minimal insertion losses.
|
