POLYPHASE SYNCHRONIZING CIRCUIT

摘要

PURPOSE:To prevent effect of an error onto a data signal in a frame even when a frame bit is detected in error by providing a frame bit phase latch circuit. CONSTITUTION:A frame bit detection circuit 1 detects a frame bit F from a data signal, a frame bit phase latch circuit 2 latches a frame period based on a phase of the frame bit F to output a reference frame bit FR. A reset signal generating circuit 3 generates a reset signal based on the phase of the reference frame bit FR. A clock signal extracted from a data signal by a phase synchronization 4, only a data signal identification clock signal for waveform overlap and spread part of the data signal is shifted by using the reset signal at a clock phase shift circuit 5. Thus, even when a frame bit is detected in error, malfunction of the reset signal generating circuit 3 and the clock phase shift circuit 5 is prevented and the effect of an error onto a data signal in the frame is prevented.