| 摘要 |
PURPOSE:To improve the accuracy and the resolution capacity, by converting a clock signal to a pulse in accordance with the magnitude relaton to counting and outputting it. CONSTITUTION:This circuit is provided with upper and lower limit logical operation circuits for detecting the upper and lower limits of a counting value of a digital counter 5 for counting a pulse input signal based on a clock signal, and at the time of an output of the second gate, an up or down pulse is outputted to an up-down counter 23, and a state N of the counter 23 is decided. Also, a variable frequency dividing counter 24 counts an output SCL of a clock oscillator 13, converts 1 pulse to a new clock signal SCLN at every N pulse, and outputs it from a terminal 25. Accordingly, the counter 5 is always maintained in an optimum state. |
